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Day 20: Floorplanning and Placement in VLSI Design

Dec 22, 20243 min read

Welcome to Day 20! Today, I explored Floorplanning and Placement, key stages in the physical design process of VLSI. These steps are fundamental to...

Day 20: Floorplanning and Placement in VLSI Design

Day 18: Design for Testability (DFT) in VLSI

Dec 20, 20243 min read

Welcome to Day 18! Today’s focus was on Design for Testability (DFT), an essential aspect of VLSI design aimed at ensuring chips are easy to test and...

Day 18: Design for Testability (DFT) in VLSI

Day 14: Advanced Floorplanning Strategies in VLSI Design

Dec 16, 20243 min read

Mastering Advanced Floorplanning: Optimizing Chip Layout for Performance, Power, and Scalability · Welcome to Day 14! Today’s focus was on advanced...

Day 14: Advanced Floorplanning Strategies in VLSI Design

Day 13: VLSI Design Flow - From RTL to GDSII

Dec 15, 20243 min read

From Code to Silicon: Unraveling the VLSI Design Flow from RTL to GDSII · Welcome to Day 13! Today, I explored the VLSI Design Flow, the complete process...

Day 13: VLSI Design Flow - From RTL to GDSII

Day 12: Power-Aware Floorplanning and Layout Optimization

Dec 14, 20243 min read

Enhancing Efficiency: Power-Aware Floorplanning and Layout Strategies in VLSI Design · Welcome to Day 12! Today, I explored the intricate world of...

Day 12: Power-Aware Floorplanning and Layout Optimization

Day 11: Low-Power Design Techniques in Digital and Mixed-Signal Systems

Dec 13, 20243 min read

Optimizing Efficiency: Exploring Low-Power Design Techniques in Modern Electronics · Welcome back! On Day 11, I explored one of the most critical...

Day 11: Low-Power Design Techniques in Digital and Mixed-Signal Systems