Deep Learning vs Physics-Informed Neural Networks (PINNs): Revolutionizing VLSI Design
Chandrakiran G
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25 posts published so far
Day 23: Timing Analysis and Closure in VLSI Design
Chandrakiran G
Day 22: Routing in VLSI Design
Chandrakiran G
Day 21: Clock Tree Synthesis (CTS) in VLSI Design
Chandrakiran G
Day 20: Floorplanning and Placement in VLSI Design
Chandrakiran G
Day 19: Static Timing Analysis (STA) in VLSI
Chandrakiran G
Day 18: Design for Testability (DFT) in VLSI
Chandrakiran G
Day 17: Low Power Design Techniques in VLSI
Chandrakiran G
Day 16: Multi-Clock Domain Designs and Clock Domain Crossing (CDC)
Chandrakiran G
Day 15: Introduction to Clock Tree Synthesis (CTS) in VLSI Design
Chandrakiran G
Day 14: Advanced Floorplanning Strategies in VLSI Design
Chandrakiran G
Day 13: VLSI Design Flow - From RTL to GDSII
Chandrakiran G
Day 12: Power-Aware Floorplanning and Layout Optimization
Chandrakiran G
Day 11: Low-Power Design Techniques in Digital and Mixed-Signal Systems
Chandrakiran G
Day 10: Timing Analysis and Clock Management in Digital Systems
Chandrakiran G
Day 9: Mastering the Fundamentals of Analog and Digital Electronics – A Deep Dive
Chandrakiran G
Day 8: Bridging Digital and Analog Electronics – Exploring FPGA Applications
Chandrakiran G
Day 7: Understanding Finite State Machines (FSMs) in Digital Design
Chandrakiran G
Day 6: Introduction to Sequential Circuits – Adding Memory to Digital Designs
Chandrakiran G
Day 5: Exploring Types of Combinational Circuits
Chandrakiran G
Day 4: Diving Into Sequential Circuits – Introducing Memory to Designs
Chandrakiran G
Day 3: Designing Combinational Circuits with CMOS Logic Gates
Chandrakiran G
Day 2: Understanding Logic Gates and Building with CMOS
Chandrakiran G
Day 1: Diving Into VLSI Design Fundamentals
Chandrakiran G
Day 0: Embarking on My VLSI Design Learning Journey
Chandrakiran G