The-VLSI-Learning-Journey

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Day 23: Timing Analysis and Closure in VLSI Design

Jan 1, 20253 min read

Day 22: Routing in VLSI Design

Dec 26, 20243 min read

Deep Learning vs Physics-Informed Neural Networks (PINNs): Revolutionizing VLSI Design

The field of Very Large Scale Integration (VLSI) is rapidly evolving with the incorporation of advanced machine learning methods. Among these, Deep Learning (DL) and Physics-Informed Neural Networks (PINNs) have emerged as powerful tools that are tra...

Sep 22, 20252 min read

Day 21: Clock Tree Synthesis (CTS) in VLSI Design

Dec 23, 20243 min read

Day 20: Floorplanning and Placement in VLSI Design

Dec 22, 20243 min read

Day 19: Static Timing Analysis (STA) in VLSI

Welcome to Day 19! Today, I delved into Static Timing Analysis (STA), a cornerstone of modern VLSI design. STA ensures that a digital design meets its timing requirements, guaranteeing reliable operation across all clock domains. Why is STA Importan...

Dec 21, 20243 min read

Day 18: Design for Testability (DFT) in VLSI

Welcome to Day 18! Today’s focus was on Design for Testability (DFT), an essential aspect of VLSI design aimed at ensuring chips are easy to test and debug during production. As designs become more complex, DFT techniques help maintain quality and re...

Dec 20, 20243 min read

Day 17: Low Power Design Techniques in VLSI

Welcome to Day 17! Today, I delved into Low Power Design Techniques—a critical aspect of VLSI design aimed at reducing power consumption while maintaining performance and functionality. With the rise of mobile and IoT devices, power efficiency has be...

Dec 19, 20243 min read